The present invention relates to a field effect transistor of the enhancement type operating in ultra-high frequencies, in which the control electrode has a metal--insulator--metal structure. The first metal ensures a Schottky contact with the active layer of the transistor, the insulator or dielectric having a controlled dielectric leak and the second metal constituting the control gate to which the bias voltage is applied.
The technology of integrated circuits on high-speed materials, such as GaAs, more particularly, uses as the active elements Schottky gate-type field effect transistors. In such transistors, the gate is constituted by a metallization or metal coating ensuring a Schottky contact with the active layer of the transistor on which it is deposited. These transistors are frequently called MESFET's, i.e. metal semiconductor field effect transistors.
MESFET's can operate in the depletion mode, for which the gate voltage is negative, the space charge zone located beneath the gate modulating the channel between the input electrodes of the transistor, i.e. the source and drain. They can also operate in the limited enhancement mode. There is a depleted area for a zero gate voltage and this area can be reduced by applying a low positive voltage V.sub.G to the gate. This positive voltage is limited by the height of the metal--semiconductor barrier, in energy diagrams, to a value close to +0.6 V, beyond which the gate starts to leak significantly.
For logics applications, it is desirable to be able to work in the enhancement mode, particularly if it is possible to pinch-off the channel between the source and drain for a zero gate voltage, i.e. with normally blocked transistors. The construction of normally blocked MESFET's is limited by the value of +0.6 V on GaAs as a result of gate leakage.
An apparently possible solution, namely that of MOS transistors on GaAs suffers from serious instability problems due to the interface states between the metal, insulating and semiconductor layers, which charge and discharge. This instability leads to displacements of the capacitance curve as a function of the voltage, the capacitance being formed by the gate metallization, the oxide layer and the semiconductor layer, after biasing and to a reduction in the transconductance when the transistors are operated at low frequencies.
These difficulties are solved by using a capacitively coupled field effect transistor gate, the dielectric of the gate capacitance having a slight controlled leak, which is adequate to make it possible to maintain in electrical balance the two metal coatings constituting the gate of the transistor according to the invention, but sufficiently low to limit the current of the diode formed between the gate and the active layer of the transistor, said limitation making it possible to operate up to +1.5 V bias.